Neural Comp. Sign up for ETOCS
HOME HELP FEEDBACK SUBSCRIPTIONS ARCHIVE SEARCH TABLE OF CONTENTS
 QUICK SEARCH:   [advanced]


     


This Article
Right arrow Full Text
Right arrow Full Text (PDF)
Right arrow Alert me when this article is cited
Right arrow Alert me if a correction is posted
Services
Right arrow Similar articles in this journal
Right arrow Alert me to new issues of the journal
Right arrow Download to citation manager
Right arrow reprints & permissions
Citing Articles
Right arrow Citing Articles via Google Scholar
Google Scholar
Right arrow Articles by Vogelstein, R. J.
Right arrow Articles by Etienne-Cummings, R.
Right arrow Search for Related Content
PubMed
Right arrow Articles by Vogelstein, R. J.
Right arrow Articles by Etienne-Cummings, R.
(Neural Computation. 2007;19:2281-2300.)
© 2007 The MIT Press

A Multichip Neuromorphic System for Spike-Based Visual Information Processing

R. Jacob Vogelstein

jvogelst{at}jhu.edu Department of Biomedical Engineering, Johns Hopkins University, Baltimore, MD 21205, U.S.A.

Udayan Mallik

udayan{at}gmail.com Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218, U.S.A.

Eugenio Culurciello

eugenio.culurciello{at}yale.edu Department of Electrical Engineering, Yale University, New Haven, CT 06511, U.S.A.

Gert Cauwenberghs

gert{at}ucsd.edu Division of Biological Sciences, University of California, San Diego, La Jolla, CA 92093, U.S.A.

Ralph Etienne-Cummings

retienne{at}jhu.edu Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218, U.S.A.

We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 x 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.







HOME HELP FEEDBACK SUBSCRIPTIONS ARCHIVE SEARCH TABLE OF CONTENTS
J COGNITIVE NEUROSCIENCE NEURAL COMPUTATION MIT PRESS JOURNALS
Copyright © 2007 by The MIT Press.